NSGA-based parasitic-aware optimization of a 5GHz low-noise VCO
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Classification of analog synthesis tools based on their architecture selection mechanisms
Integration, the VLSI Journal
Automated design and optimization of low-noise oscillators
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2009 International Conference on Computer-Aided Design
Modeling and characterization of a 5.2 GHz VCO for UWB applications in 0.13 μm CMOS process
Analog Integrated Circuits and Signal Processing
Generation of surrogate models of Pareto-optimal performance trade-offs of planar inductors
Analog Integrated Circuits and Signal Processing
Optimal LC-VCO design through evolutionary algorithms
Analog Integrated Circuits and Signal Processing
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This paper presents a specification-driven layout-aware CMOS RF LC-oscillator design tool called CYCLONE. Circuit sizing and layout generation are integrated in the overall oscillator optimization. The tool optimizes the device sizes and also determines the optimal geometrical parameters of the on-chip inductor and automatically performs electromagnetic simulations to exactly calculate its losses during sizing. For the other devices in the oscillator circuit, being gain cell and varactor diode, it uses a technology-independent template-based layout generation approach to obtain accurate predictions of the actual layout parasitics. The device sizing of the gain cell is based on an operating-point linearized BSIM3 model of the gain cell transistors. The varactor diode is sized based on the BSIM3 source/drain diode models of the pMOS transistor. All parasitics; are incorporated in a global optimization of the complete oscillator circuit. After optimization of the circuit, the layout can be exported to a standard GDSII format for processing. The capabilities of the tool are demonstrated by several design experiments.