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Boolector: An Efficient SMT Solver for Bit-Vectors and Arrays
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A Gröbner basis approach to CNF-formulae preprocessing
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A lazy and layered SMT(BV) solver for hard industrial verification problems
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A fast linear-arithmetic solver for DPLL(T)
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Equivalence Verification of Polynomial Datapaths Using Ideal Membership Testing
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Modular equivalence verification of polynomial datapaths with multiple word-length operands
HLDVT '11 Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop
SMTInterpol: an interpolating SMT solver
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In formal verification, proof logging is a technique for automatically reviewing the reasoning steps of a proof engine by a separate tool. This is useful for enhancing the confidence in the prover's result, especially in the case of a positive answer when no counterexample exists. Mature proof logging techniques exist for single-theory provers. SMT solvers, however, combine several theories so that developing an unified proof logging technique is more challenging. This paper proposes an approach for logging the proofs of the SMT solver STABLE which is a prover combining SAT and computer algebra engines. We show how to translate the SAT proofs into algebraic forms (polynomials) and how to check the combined Boolean and word-level proofs using a separate computer algebra engine.