Design with Operational Amplifiers and Analog Integrated Circuits
Design with Operational Amplifiers and Analog Integrated Circuits
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
Design and implementation of an all-CMOS 802.11a wireless LAN chipset
IEEE Communications Magazine
| Hi-index | 0.00 |
This paper presents an analog to digital converter (ADC) architecture suitable for wideband wireless receiver system. The in-phase (I) and quadrature (Q) ADCs work independently, but share on-chip reference buffer and non-overlapped clock generation block for balance between two channels. The single ADC core consists of one front sample and hold amplifier, four cascade of 2.5 bit pipeline stages with pseudo-class AB opamp shared between adjacent stages and one 2 bit backend flash stage. The prototype was fabricated in standard 130 nm CMOS process and occupied silicon area of 0.62 mm2. Performance of 66 dB spurious-free-dynamic-range is measured at 80 MS/s with 1 Vpp input signal. The power dissipation of the whole chip is only 53 mW from a 1.1 V supply.