A survey of design techniques for system-level dynamic power management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Challenges in Embedded Memory Design and Test
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A Complete Memory Address Generator for Scan Based March Algorithms
MTDT '05 Proceedings of the 2005 IEEE International Workshop on Memory Technology, Design, and Testing
Low Transition LFSR for BIST-Based Applications
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reducing SRAM power using fine-grained wordline pulsewidth control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DS-LFSR: a BIST TPG for low switching activity
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BIST-Based Fault Diagnosis for Read-Only Memories
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Novel Heuristic Method for Application-Dependent Testing of a SRAM-Based FPGA Interconnect
IEEE Transactions on Computers
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In the ongoing high-speed, high-tech sophistication in the technology of VLSI designs, Built-in Self-Test (BIST) is emerging as the essential element of the memory, which can be treated as the most essential ingredient of the System on Chip. The market is flooded with diverse algorithms exclusively intended for investigating the memory locations. LFSRs (Linear Feedback Shift Register) are employed extensively for engendering the memory addresses, so that they can be consecutively executed on the memory cores under experimentation. What we have attempted to put forward through this paper is a proposed LFSR based address generator with significant decrease in switching process for low power MBIST (Memory Built in Self Test). In this novel technique, the address models are produced by a blend of LFSR and a 2-bit pattern generator (Modified LFSR) and two distinct clock signals. With the efficient employ of the adapted architecture switching activity is considerably cut down. As the switching activity is in direct proportion to the power consumed scaling down the switching process of the address generator inevitably leads to the reduction in power consumption of the MBIST. In this paper we have taken pains to design and stimulate the proposed address generator by means of Xilinx ISE tools and contrasted it with the switching activities of the conventional LFSR and BS-LFSR (Bit Swapping Linear Feedback Shift Register). The encouraging outcomes illustrate a significant reduction in switching activity, to the tune of 90 % plus of the entire dynamic power in relation to the traditional LFSR.