An improved RC model for VLSI interconnects with applications to buffer insertion

Authors:
Alaa R. Al-Taee;Fei Yuan;Andy Ye
Affiliations:
Department of Electrical and Computer Engineering, Ryerson University, Toronto, Canada;Department of Electrical and Computer Engineering, Ryerson University, Toronto, Canada;Department of Electrical and Computer Engineering, Ryerson University, Toronto, Canada
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2014

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Abstract

A general platform to generate the RC, RLC and RLCG models of interconnects using global approximation method, two-port networks, and asymptotic waveform evaluation (AWE) is presented. Using the delay of transmission-line-modeled interconnects from HSPICE as a bench mark, we show that among all 18 models studied, the 驴-configuration of AWE-RLC model yields the best accuracy. To reduce complexity subsequently computational cost without sacrificing accuracy, the AWE-RLC model is mapped to a complex RC model using moment matching. The complex RC model is further mapped to an improved RC model utilizing the principle of charge reservation. The improved RC model is employed to estimate the delay of long interconnects with buffer insertion. As compared with the conventional RC model, the improved RC model reduces the delay of interconnects with buffer insertion, the number of buffers, and the size of the buffer by 20.5, 24, and 32 %, respectively.