Timing verification of sequential domino circuits

Authors:
David Van Campenhout;Trevor Mudge;Karem A. Sakallah
Affiliations:
Advanced Computer Architecture Laboratory, EECS Department, University of Michigan, Ann Arbor, Michigan;Advanced Computer Architecture Laboratory, EECS Department, University of Michigan, Ann Arbor, Michigan;Advanced Computer Architecture Laboratory, EECS Department, University of Michigan, Ann Arbor, Michigan
Venue:
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Year:
1997

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Abstract

Two methods are presented for static timing verification of sequential circuits implemented as a mix of static and domino logic. Constraints for proper operation of domino gates are derived. An important observation is that input signals to domino gates may start changing near the end of the evaluate phase. The first method models domino gates explicitly, similar to latches. The second method treats domino gates only during pre- and post-processing steps. This method is shown to be more conservative, but easier to compute.