Optimal interconnect diagnosis of wiring networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A New Diagnosis Approach for Short Faults in Interconnects
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
On the Fault Coverage of Interconnect Diagnosis
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Testing Layered Interconnection Networks
IEEE Transactions on Computers
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This paper presents a new approach for diagnosing stuck-at and short faults in interconnects whose layouts are known. This structural approach exploits different graph coloring and coding techniques to generate a test set with no aliasing and confounding. The conditions for aliasing and confounding are analyzed with respect to the size and number of the shorts in the fault set. The characteristics of unbalanced/balanced codes for encoding the colors in the vector generation process for interconnect diagnosis are discussed and proved using a novel algebra. An algorithm for diagnosis is then presented.