Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
Intel iPSC concurrent computer
Programming parallel processors
Hardware reconfiguration of transputer networks for distributed object-oriented programming
Microprocessing and Microprogramming
Proceedings of the world transputer user group (WOTUG) conference on Transputing '91
BYTE
The cube-connected cycles: a versatile network for parallel computation
Communications of the ACM
Ethernet: distributed packet switching for local computer networks
Communications of the ACM
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This paper presents the development and the performance of a novel bus-based message passing interconnection scheme which can be used to join a large number of INMOS Transputers via their serial communication links [1]. The main feature of this architecture is that it avoids the communication overhead which occurs in systems where processing nodes relay communications to their neighbors. It also produces a flexible and scalable machine whose attractive characteristics are its simplicity and low latency for large configurations. We will show that this architecture is free from deadlock, exhibits much smaller latency than most directly connected Transputer networks and has a scalable bandwidth, in contrast to other bus topologies.