Substrate noise influence on circuit performance in variable threshold-voltage scheme

Authors:
Tadahiro Kuroda;Tetsuya Fujita;Shinji Mita;Toshiaki Mori;Kenji Matsuo;Masakazu Kakumu;Takayasu Sakurai
Affiliations:
System ULSI Engineering Laboratory, Toshiba Corp., Kawasaki, Japan;System ULSI Engineering Laboratory, Toshiba Corp., Kawasaki, Japan;System ULSI Engineering Laboratory, Toshiba Corp., Kawasaki, Japan;Semiconductor Group, Toshiba Corp., Kawasaki, Japan;Semiconductor Group, Toshiba Corp., Kawasaki, Japan;Semiconductor Group, Toshiba Corp., Kawasaki, Japan;System ULSI Engineering Laboratory, Toshiba Corp., Kawasaki, Japan
Venue:
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Year:
1996

Low-power CMOS design through VTH control and low-swing circuits

ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
A low power CMOS circuit with Variable Souce Scheme (VSCMOS)

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Clock delayed domino logic with efficient variable threshold voltage keeper

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Hi-index	0.00