ACM Transactions on Programming Languages and Systems (TOPLAS)
Parallel discrete event simulation
Communications of the ACM - Special issue on simulation
A sweep algorithm for massively parallel simulation of circuit-switched networks
Journal of Parallel and Distributed Computing - Special issue on parallel and discrete event simulation
A parallel simulator for performance modelling of broadband telecommunication networks
WSC '92 Proceedings of the 24th conference on Winter simulation
GTW: a time warp system for shared memory multiprocessors
WSC '94 Proceedings of the 26th conference on Winter simulation
Using time warp for computer network simulations on transputers
ANSS '91 Proceedings of the 24th annual symposium on Simulation
Conservative simulation of load-balanced routing in a large ATM network model
PADS '98 Proceedings of the twelfth workshop on Parallel and distributed simulation
Efficient Execution of Time Warp Programs on Heterogeneous, NOW Platforms
IEEE Transactions on Parallel and Distributed Systems
Partitioning WCN models for parallel simulation of radio resource management
Wireless Networks - Special issue: Design and modeling in mobile and wireless systsems
Controlling over-optimism in time-warp via CPU-based flow control
WSC '04 Proceedings of the 36th conference on Winter simulation
Warp speed: executing time warp on 1,966,080 cores
Proceedings of the 2013 ACM SIGSIM conference on Principles of advanced discrete simulation
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Most existing synchronization protocols require that the simulation application be partitioned and mapped to logical processes to make it suitable for parallel execution. Assuming the simulation models some number of physical components, an important design question is how many components should be mapped to each logical process? This is a nontrivial question because logical process "size" affects the efficiency of the synchronization protocol, load balance, and approach for implementing shared state variables, as well as the efficiency of the event processing loop within the parallel simulator. This question is studied in the context of a Time Warp-based parallel simulator. Results of two experimental studies are described that compare the performance of parallel simulators using different logical process sizes. One study uses synthetic workloads; the other uses an Asynchronous Transfer Mode (ATM) network. These results show that the choice of logical process size can have a significant effect on performance, and the optimal size depends on model size, the number of available processors, and detailed semantics of the model itself.