An investigation of operating methods for 0.25 micron semiconductor manufacturing

Authors:
James F. Hallas;Jane D. Kim;Charles T. Mosier;Carolyn Internicola
Affiliations:
Texas Instruments, East Building, Mail Station 385, P.O. Box 655012, Dallas, TX;SEMATECH, 2706 Montopolis Drive, Austin, TX;School of Business, Clarkson University, Box 5790, Potsdam, NY;SEMATECH, 2706 Montopolis Drive, Austin, TX
Venue:
WSC '96 Proceedings of the 28th conference on Winter simulation
Year:
1996

Citing 2
Cited 1

The use of bottleneck starvation avoidance with queue predictions in shop floor control

WSC '89 Proceedings of the 21st conference on Winter simulation
An investigation of operating methods for 0.25 micron semiconductor manufacturing

WSC '96 Proceedings of the 28th conference on Winter simulation

An investigation of operating methods for 0.25 micron semiconductor manufacturing

WSC '96 Proceedings of the 28th conference on Winter simulation

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Abstract

This study investigates a number of operational issues associated with the control of microprocessor fabrication facilities, specifically expanding the domain of previous research to investigate the effects of lot size, test wafer proportion, and tool productivity on wafer fabrication performance. Response variables included cost and production performance metrics.