Synchronous up/down binary counter for LUT FPGAs with counting frequency independent of counter size

  • Authors:

  • Alexandre F. Tenca;Miloš D. Ercegovac

  • Affiliations:

  • Computer Science Department, University of California, Los Angeles;Computer Science Department, University of California, Los Angeles

  • Venue:
  • FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
  • Year:
  • 1997

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Abstract

This paper presents the design of a fast binary counter for LUT FPGAs. The counter has a cycle time independent of the counter size. The key aspects of the design are described and applied to a 64-bit synchronous binary counter implemented in a XC4010 FPGA chip. Experimental results show that the counter can scale up to hundreds of bits while keeping a short cycle time.