Realization of a programmable parallel DSP for high performance image processing applications

Authors:
Jens Peter Wittenburg;Willm Hinrichs;Johannes Kneip;Martin Ohmacht;Mladen Bereković;Hanno Lieske;Helge Kloos;Peter Pirsch
Affiliations:
Laboratorium für Informationstechnologie, Universität Hannover, Schneiderberg 32, 30167 Hannover, Germany;Laboratorium für Informationstechnologie, Universität Hannover, Schneiderberg 32, 30167 Hannover, Germany;Laboratorium für Informationstechnologie, Universität Hannover, Schneiderberg 32, 30167 Hannover, Germany;Laboratorium für Informationstechnologie, Universität Hannover, Schneiderberg 32, 30167 Hannover, Germany;Laboratorium für Informationstechnologie, Universität Hannover, Schneiderberg 32, 30167 Hannover, Germany;Laboratorium für Informationstechnologie, Universität Hannover, Schneiderberg 32, 30167 Hannover, Germany;Laboratorium für Informationstechnologie, Universität Hannover, Schneiderberg 32, 30167 Hannover, Germany;Laboratorium für Informationstechnologie, Universität Hannover, Schneiderberg 32, 30167 Hannover, Germany
Venue:
DAC '98 Proceedings of the 35th annual Design Automation Conference
Year:
1998

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Abstract

Architecture and design of the HiPAR-DSP, a SIMD controlled signalprocessor with parallel data paths, VLIW and novel memory design.The processor architecture is derived from an analysis of thetarget algorithms and specified in VHDL on register transfer level.A team of more than 20 graduate students covered the whole designprocess, including the synthesizable VHDL description, synthesis,routing and backannotation as the development of a complete softwaredevelopment environment.The 175mm{2}, 0.5驴m 3LM CMOSdesign with 1.2 million transistors operates at 80 MHz and achievesa sustained performance of more than 600 million arithmetic operations.