Optimal pipelining in supercomputers
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Communications of the ACM - Special issue on computer architecture
Program Flow Analysis: Theory and Application
Program Flow Analysis: Theory and Application
Structure of Computers and Computations
Structure of Computers and Computations
The computational speed of supercomputers
SIGMETRICS '83 Proceedings of the 1983 ACM SIGMETRICS conference on Measurement and modeling of computer systems
ACM SIGARCH Computer Architecture News
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There is an apparent conflict between the hardware requirements for fast parallel execution and the hardware requirements for fast serial execution. For example, fast vector execution is achieved by maintaining high execution concurrency over extended periods of time. With many operations executing in parallel, the time to carry out individual operations is much less important than the average execution concurrency.Fast serial execution, on the other hand, requires rapid execution of relatively few operations at a time; hardware concurrency can be sacrificed in favor of short execution times. Fewer registers and memory locations are required, but they must have shorter access times than for parallel execution.We show how to integrate these seemingly conflicting requirements into a single computer, using asymmetric distribution of hardware, and sometimes using software to allocate variables to appropriate parts of the storage hierarchy.