The role of VHDL in the MCC CAD system

• Authors: Ramón D. Acosta;Mark Alexandre;Gary Imken;Bill Read
• Venue: DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
• Year: 1988

The VHSIC Hardware Description Language (VHDL), currently undergoing standardization by the IEEE, supports the hierarchical design, documentation, and simulation of a wide range of digital system abstractions. This paper describes a suite of utilities for manipulating VHDL designs that has been developed and integrated into the CAD System of the Microelectronics and Computer Technology Corporation (MCC). The MCC CAD System is a tightly integrated environment supporting the sharing of design information between heterogeneous tools via an underlying knowledge base built on top of an object-oriented distributed database. The VHDL utilities include an editing mode to provide syntactic assistance for writing VHDL, an analyzer to produce intermediate representations, a compiler to translate the intermediate representations into directly executable LISP functions, an elaborator for generating simulation models from complete designs, and a simulator for these models. Experimentation, continued development, and several important extensions to the CAD System VHDL utilities are in progress.