Modeling concepts for VLSI CAD objects
ACM Transactions on Database Systems (TODS)
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
INSIST: Interactive Simulation in Smalltalk
OOPSLA '87 Conference proceedings on Object-oriented programming systems, languages and applications
The role of VHDL in the MCC CAD system
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A structural representation for VLSI design
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Browsing in chip design database
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
An extensible object-oriented mixed-mod functional simulation system
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Semantics of CAD objects for generalized databases
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
An object-oriented, procedural database for VLSI chip planning
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Generalized Version Control in an Object-Oriented Database
Proceedings of the Fourth International Conference on Data Engineering
Complex and Composite Objects in CAD/CAM Databases
Proceedings of the Fifth International Conference on Data Engineering
Block description language (BDL): A structural description language
DAC '84 Proceedings of the 21st Design Automation Conference
ICOS: an intelligent concurrent object-oriented synthesis methodology for multiprocessor systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
POSE: a parallel object-oriented synthesis environment
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Pattern Based Curriculum for Computer Systems Engineering
CSEET '97 Proceedings of the 10th Conference on Software Engineering Education and Training
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This paper presents a System-level Design Environment(SDE) for VHDL. The object-oriented approach is used for modeling the VHDL entities, design constraints and even design patterns. We suggest the data model and its internal schema, which is suitable for the VHDL semantics. SDE allows a designer to reconfigure the designed schematic by binding its generic components to technology-specific ones. It is effectively used for version control. SDE verifies the design by dynamically checking the constraints. The standard VHDL is extended in order to represent the constraints properly.