VERIFY: a program for proving correctness of digital hardware designs
Artificial Intelligence - Special volume on qualitative reasoning about physical systems
Application of term rewriting techniques to hardware design verification
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Digital image processing
Symbolic Logic and Mechanical Theorem Proving
Symbolic Logic and Mechanical Theorem Proving
Rewrite Methods for Clausal and Non-Clausal Theorem Proving
Proceedings of the 10th Colloquium on Automata, Languages and Programming
RRL: A Rewrite Rule Laboratory
Proceedings of the 8th International Conference on Automated Deduction
Mechanical Verification of Adder Circuits using Rewrite RuleLaboratory
Formal Methods in System Design
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We describe an approach to hardware verification in the context of our recent success in formally verifying the description of an image processing chip currently under development at Research Triangle Institute. We demonstrate that our approach, which uses an implementation of an equational approach to theorem proving developed by Kapur and Narendran, can be a viable alternative to simulation. In particular, we are able to take advantage of the “recursive” nature of many circuits, such as n-bit adders, and our techniques allow verification of sequential circuits. To the best of our knowledge this is the first, time a complex sequential circuit which was not designed with formal verification specifically in mind has been verified. Finally, we describe the discovery of several design errors in the circuit description, detected during the verification attempt (the actual verification could only take place once these errors were removed), and discuss directions that future work will take. A significantly more detailed description of this work can be found in [NaSt 881].