A design methodology for synthesizing parallel algorithms and architectures
Journal of Parallel and Distributed Computing
An overview of the Penn State design system
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
IEEE Transactions on Computers
The Generation of a Class of Multipliers: Synthesizing Highly Parallel Algorithms in VLSI
IEEE Transactions on Computers
Automatic synthesis of systolic arrays from uniform recurrent equations
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
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A tool for synthesizing systolic systems is introduced. Given a hierarchical specification of the computations to be performed and hints as to how these computations are to be performed, this tool generates an analysis of the hardware required to do the computations. The computations are specified as directed acyclic graphs and the hints tell the temporal and topological relationships of each computation. The systolic system is synthesized by traversing the graph and marking each computation with a processor name and a time stamp. This tool, called DECOMPOSER, is the newest entry in a tool set currently under development at Penn State [IO1]. Its output can subsequently be fed to the remaining tools in the tool set to generate a VLSI fabrication description of the systolic system.