SMART: tools and methods for synthesis of VLSI chips with processor architecture

Authors:
T. Bergstraesser;J. Gessner;K. Hafner;S. Wallstab
Affiliations:
Siemens AG, Corporate Laboratories for Information Technology, P.O. Box 830953, D-8000 Munich 83, FRG;Siemens AG, Corporate Laboratories for Information Technology, P.O. Box 830953, D-8000 Munich 83, FRG;Siemens AG, Corporate Laboratories for Information Technology, P.O. Box 830953, D-8000 Munich 83, FRG;Siemens AG, Corporate Laboratories for Information Technology, P.O. Box 830953, D-8000 Munich 83, FRG
Venue:
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Year:
1988

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Abstract

A design environment supporting processor synthesis in data path style is presented in this paper. The programming model of a processor described in Common Lisp is transformed into a hardware structure by means of tools integrated into this environment. The generation of alternative designs is supported by the interactive graphical manipulation of behavior and hardware structure representations and their correspondences. The synthesis procedure is explained using an example.