Parallel program design: a foundation
Parallel program design: a foundation
Communication and concurrency
Temporal logic for real time systems
Temporal logic for real time systems
STATEMATE: A Working Environment for the Development of Complex Reactive Systems
IEEE Transactions on Software Engineering
On the development of reactive systems
Logics and models of concurrent systems
Multilevel specification of real time systems
Communications of the ACM - Special issue on software engineering
CCS + time = an interleaving model for real time systems
Proceedings of the 18th international colloquium on Automata, languages and programming
The temporal logic of reactive and concurrent systems
The temporal logic of reactive and concurrent systems
Guest A Layered Approach to Automating the Verification of Real-Time Systems
IEEE Transactions on Software Engineering - Special issue: specification and analysis of real-time systems
A logical approach to discrete math
A logical approach to discrete math
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Compositional verification of reactive and real-time systems
Compositional verification of reactive and real-time systems
ACM Transactions on Programming Languages and Systems (TOPLAS)
Modechart: A Specification Language for Real-Time Systems
IEEE Transactions on Software Engineering
Formal Verification for Fault-Tolerant Architectures: Prolegomena to the Design of PVS
IEEE Transactions on Software Engineering
Real-time symbolic model checking for discrete time models
Theories and experiences for real-time system development
Software requirements & specifications: a lexicon of practice, principles and prejudices
Software requirements & specifications: a lexicon of practice, principles and prejudices
On using temporal logic for refinement and compositional verification of concurrent systems
AMAST '93 Selected papers of the international conference on Algebraic methodology of software technology
Verifying clocked transition systems
Proceedings of the DIMACS/SYCON workshop on Hybrid systems III : verification and control: verification and control
IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
Model reduction of modules for state-event temporal logics
IFIP TC6/ 6.1 international conference on formal description techniques IX/protocol specification, testing and verification XVI on Formal description techniques IX : theory, application and tools: theory, application and tools
Verifying properties of parallel programs: an axiomatic approach
Communications of the ACM
Deciding Properties of Timed Transition Models
IEEE Transactions on Parallel and Distributed Systems
Proving Properties of Real-Time Systems Through Logical Specifications and Petri Net Models
IEEE Transactions on Software Engineering
A Formal Framework for ASTRAL Intralevel Proof Obligations
IEEE Transactions on Software Engineering
Automatic Symbolic Verification of Embedded Systems
IEEE Transactions on Software Engineering
Correctness of Real Time Systems by Construction
ProCoS Proceedings of the Third International Symposium Organized Jointly with the Working Group Provably Correct Systems on Formal Techniques in Real-Time and Fault-Tolerant Systems
Compositionality and Modularity in Process Specification and Design: A Trace-State Based Approach
Temporal Logic in Specification
The NCSU Concurrency Workbench
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Timed CSP: Theory and Practice
Proceedings of the Real-Time: Theory in Practice, REX Workshop
Forward and Backward Simulations for Timing-Based Systems
Proceedings of the Real-Time: Theory in Practice, REX Workshop
STeP: The Stanford Temporal Prover
STeP: The Stanford Temporal Prover
Parallel Refinement Mechanisms for Real-Time Systems
FASE '00 Proceedings of the Third Internationsl Conference on Fundamental Approaches to Software Engineering: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
On Verification of Refinements of Timed Distributed Algorithms
ASM '00 Proceedings of the International Workshop on Abstract State Machines, Theory and Applications
Towards integrated verification of timed transition models
Fundamenta Informaticae - Special issue on application of concurrency to system design (ACSD'04)
Automated compositional proofs for real-time systems
Theoretical Computer Science
Modeling time in computing: A taxonomy and a comparative survey
ACM Computing Surveys (CSUR)
Automated compositional proofs for real-time systems
FASE'05 Proceedings of the 8th international conference, held as part of the joint European Conference on Theory and Practice of Software conference on Fundamental Approaches to Software Engineering
Towards Integrated Verification of Timed Transition Models
Fundamenta Informaticae - APPLICATION OF CONCURRENCY TO SYSTEM DESIGN (ACSD'04)
Bounded satisfiability checking of metric temporal logic specifications
ACM Transactions on Software Engineering and Methodology (TOSEM) - In memoriam, fault detection and localization, formal methods, modeling and design
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Reactive systems exhibit ongoing, possibly nonterminating, interaction with the environment. Real-time systems are reactive systems that must satisfy quantitative timing constraints. This paper presents a structured compositional design method for discrete real-time systems that can be used to combat the combinatorial explosion of states in the verification of large systems. A composition rule describes how the correctness of the system can be determined from the correctness of its modules, without knowledge of their internal structure. The advantage of compositional verification is clear. Each module is both simpler and smaller than the system itself. Composition requires the use of both model-checking and deductive techniques. A refinement ruleguarantees that specifications of high-level modules are preserved by their implementations. The StateTime toolset is used to automate parts of compositional designs using a combination of model-checking and simulation. The design method is illustrated using a reactor shutdown system that cannot be verified using the StateTime toolset (due to the combinatorial explosion of states) without compositional reasoning. The reactor example also illustrates the use of the refinement rule.