A self-routing permutation network
Journal of Parallel and Distributed Computing
Fast Self-Routing Permutation Switching on an Asymptotically Minimum Cost Network
IEEE Transactions on Computers
Design and analysis of a novel fast packet switch: pipeline Banyan
IEEE/ACM Transactions on Networking (TON)
A Fast VLSI-Efficient Self-Routing Permutation Network
IEEE Transactions on Computers
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In this paper, we present a new implementation of the fast VLSI-efficient self-routing N 脳 N permutation network proposed by Cam and Fortes, which requires only about half as much hardware and has a lower latency. Cam and Fortes' implementation uses Cormen and Leiserson's hyperconcentrators, which can route only active inputs. The reduction in hardware is achieved by modifying Cormen and Leiserson's hyperconcentrator to route active, as well as inactive, inputs to the output. This modification allows us to reduce the number of hyperconcentrators needed in the permutation network by 50 percent and eliminate the interstage interconnection networks, making the permutation network faster by log2N bits.