A Fast VLSI-Efficient Self-Routing Permutation Network

  • Authors:
  • Jose A. B. Fortes;Hasan Cam

  • Affiliations:
  • -;-

  • Venue:
  • IEEE Transactions on Computers
  • Year:
  • 1995

Quantified Score

Hi-index 14.99

Visualization

Abstract

A multistage self-routing permutation network is presented. This network is constructed from concentrators and digit-controlled $2 \times 4$ switches. A destination-tag routing scheme is used to realize any arbitrary permutation. The network has $O(log^2\ N)$ gate-delay and uses $O(N^2)$ VLSI-area, where N is the number of inputs.1 Assuming packet-switching is used for message transmission, the delay and VLSI-area of the network are smaller than those of any self-routing permutation network presented to date.