Reducing energy in instruction caches by using multiple line buffers with prediction
ISHPC'05/ALPS'06 Proceedings of the 6th international symposium on high-performance computing and 1st international conference on Advanced low power systems
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This paper describes an on-chip cache, called a separated bit-line unified cache, which minimizes the chip-area cost in high-performance microprocessors. This unified cache has two ports; one for the instruction bus and the other for the data bus. A separated bit-line memory hierarchy architecture realizes memory hierarchy design with only 10%-20% area overhead. The total cache area can be reduced by more than 20%-30% on the average at capacities of larger than 64 KB with the same hit rate as the conventional cache. The cache latency reaches 4.2 ns at a supply voltage of 1 V. Additionally, the cache is physically addressable even if the cache has a large capacity.