IEEE Transactions on Computers
A radix-8 wafer scale FFT processor
Journal of VLSI Signal Processing Systems - Special issue: 1990 Workshop on VLSI signal processing
An expandable column FFT architecture using circuit switching networks
Journal of VLSI Signal Processing Systems
On computing the fast Fourier transform
Communications of the ACM
High Speed DCT/IDCT Using a Pipelined CORDIC Algorithm
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
AAECC'07 Proceedings of the 17th international conference on Applied algebra, algebraic algorithms and error-correcting codes
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This paper presents a new fast Discrete Fourier Transform (DFT)algorithm. By rewriting the DFT, a new algorithm is obtained that uses2n−2(3n−13)+4n−2 real multiplications and 2n−2(7n−29)+6n+2real additions for a real data N=2n point DFT, comparable to the number of operations in the Split-Radix method, but with slightly fewer multiply and add operations in total. Because of the organization of multiplications as plane rotations in this DFT algorithm, it ispossible to apply a pipelined CORDIC algorithm in a hardwareimplementation of a long-point DFT, e.g., at a 100 MHz input rate, a1024-point transform can be realized with a 200 MHz clocking of a singleCORDIC pipeline.