On a case of symbiosis between systolic arrays
Integration, the VLSI Journal
VLSI computations: from physics to algorithms
Integration, the VLSI Journal
IEEE Transactions on Computers
A radix-8 wafer scale FFT processor
Journal of VLSI Signal Processing Systems - Special issue: 1990 Workshop on VLSI signal processing
An expandable column FFT architecture using circuit switching networks
Journal of VLSI Signal Processing Systems
A chip set for pipeline and parallel pipeline FFT architectures
Journal of VLSI Signal Processing Systems - Special issue on the Canadian conference on VLSI
The cube-connected cycles: a versatile network for parallel computation
Communications of the ACM
Efficient Systolic Arrays for FFT Algorithms
ASILOMAR '95 Proceedings of the 29th Asilomar Conference on Signals, Systems and Computers (2-Volume Set)
Computational Aspects of VLSI
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An expandable two-dimensional systolic array consisting of N homogeneousprocessing elements in a rectangular sturcture to compute the one-dimensional DFT transform is proposed.DFT of size N = M^2 can be computed in 2M steps ofpipelined operations, achieving the optimal Area–Time complexityof AT^2 = O(N^2). The architecture is based on a new approachthat exploits the symbiosis between the one-dimensional systolicarrays of Kung [6] and Chang [7]. After atwo-dimensional formulation with Common Factor Algorithm,recursive time and frequency extractions are applied to thecolumn and row transforms respectively. Twiddle factormultiplication is integrated gracefully into the row recursion.The rearrangement of the input data enables the recursiveoperations to be pipelined orthogonally in the “dual-mode”processing elements. The proposed array structure is modular andexpandable. A DFT of size 2^LN can be readily computed with 2^L N-size arrays abutted together without reconfiguration.VHDL modules have been written and simulated successfully forthe proposed architecture.