SEFOP: a novel approach to data path module placement
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Vanguard: a chip physical design system
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
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A hierarchical gate array architecture and associated design methodology are presented. The hierarchical architecture has several advantages over conventional flat structures. A high gate density is achieved by separately optimizing local and global routing tradeoffs. Associated with the physical hierarchy is a hierarchical layout methodology, which reduces the difficulty of placement and routing by decomposing the process into several small independent operations. The architecture is optimized for fast processing and low cost by using a single level of E-beam direct-write programmable interconnect. The hierarchical placement and routing methodology is presented with results of placement and routing test cases. Finally, future enhancements are discussed.