A asynchronous buffering network for tightly coupled multiprocessors

Authors:
Yvon Jegou;Andre Seznee
Affiliations:
IRISA/INRIA, Campus de Beaulieu, 35042 Rennes Cedex, France;IRISA/INRIA, Campus de Beaulieu, 35042 Rennes Cedex, France
Venue:
ICS '89 Proceedings of the 3rd international conference on Supercomputing
Year:
1989

Citing 6
Cited 0

Synchronizing processors through memory requests in a tightly coupled multiprocessor

ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Towards a large number of pipeline processors in a tightly coupled multiprocessor using no cache

ICS '88 Proceedings of the 2nd international conference on Supercomputing
Performance of Multiprocessor Interconnection Networks

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Computer Architecture and Parallel Processing
Processor-memory interconnections for multiprocessors

ISCA '79 Proceedings of the 6th annual symposium on Computer architecture

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Abstract

In order to reach high performance, many levels of parallelism should be exploited simultaneously on massively parallel architectures. The efficiency of a large system heavily depends on the interconnection between the processing elements and the memories: asynchronous buffering networks allow a high throughput of requests when independent tasks are run, but a strict control of the network is necessary for fine grain parallelism.We show that the ordering of the requests delivery can be controlled by a simple mechanism on an asynchronous buffering interconnection network, the @@@@ network. This network is shown to be efficient in various situations as MIMD, micro-tasked, vector and pipelined computations.