Data synchronized pipeline architecture: pipelining in multiprocessor environments
Journal of Parallel and Distributed Computing
Computer Architecture and Parallel Processing
Computer Architecture and Parallel Processing
Towards a large number of pipeline processors in a tightly coupled multiprocessor using no cache
ICS '88 Proceedings of the 2nd international conference on Supercomputing
GTS: parallelization and vectorization of tight recurrences
Proceedings of the 1989 ACM/IEEE conference on Supercomputing
Characterizing the behavior of sparse algorithms on caches
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
A asynchronous buffering network for tightly coupled multiprocessors
ICS '89 Proceedings of the 3rd international conference on Supercomputing
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To satisfy the growing need for computing power, a high degree of parallelism will be necessary in future supercomputers. Up to the late 70s, supercomputers were either multiprocessors (SIMD-MIMD) or pipelined monoprocessors. Current commercial products combine these two levels of parallelism.Effective performance will depend on the spectrum of algorithms which is actually run in parallel. In a previous paper [Je86], we have presented the DSPA processor, a pipeline processor which is actually performant on a very large family of loops.In this paper, we present the GREEDY network, a new interconnection network (IN) for tightly coupled multiprocessors (TCMs). Then we propose an original and cost effective hardware synchronization mechanism. When DSPA processors are connected with a shared memory through a GREEDY network and synchronized by our synchronization mechanism, a very high parallelism may be achieved at execution time on a very large spectrum of loops including loops where independency of the successive iterations cannot be checked at compile time as e.g. loop 1:DO 1 I=1 N1 A(P(I)=A(Q(I))