A large scale cellular array processor: AAP-1

Authors:
Toshio Kondo;Tayoshi Nakashima;Toshio Tsuchiya;Yoshi Sugiyama;Tsuneta Sudo
Affiliations:
Atsugi Electrical Communication Laboratory, Nippon Telegraph and Telephone Public Corporation, 1839, Ono, Atsugi-shi, Kanagawa, 243-01, Japan;Atsugi Electrical Communication Laboratory, Nippon Telegraph and Telephone Public Corporation, 1839, Ono, Atsugi-shi, Kanagawa, 243-01, Japan;Atsugi Electrical Communication Laboratory, Nippon Telegraph and Telephone Public Corporation, 1839, Ono, Atsugi-shi, Kanagawa, 243-01, Japan;Atsugi Electrical Communication Laboratory, Nippon Telegraph and Telephone Public Corporation, 1839, Ono, Atsugi-shi, Kanagawa, 243-01, Japan;Atsugi Electrical Communication Laboratory, Nippon Telegraph and Telephone Public Corporation, 1839, Ono, Atsugi-shi, Kanagawa, 243-01, Japan
Venue:
CSC '85 Proceedings of the 1985 ACM thirteenth annual conference on Computer Science
Year:
1985

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Abstract

A SIMD cellular array processor called the Adaptive Array Processor (AAP-1) has been developed. Its 256 x 256 array of bit-organized processing elements (PEs) is composed of 1024 custom nMOS LSIs and occupies the small volume of 0.33m3. Extensive parallelism offers ultra-high throughout for various types of two-dimensional data processing, together with data-dependent operation capability through the use of control registers in each PE. The processing speed has experimentally exceeded that of a 1 MIPS sequential computer by a factor of approximately 100 for LSI design automation methods such as logic simulation, wire routing and device placement.