Assessing merged DRAM/logic technology

Authors:
Yong-Bin Kim;Tom W. Chen
Affiliations:
Univ. of Utah, Salt Lake City, UT;Colorado State Univ., Fort Collins, CO
Venue:
Integration, the VLSI Journal
Year:
1999

Citing 0
Cited 1

Pragmatic integration of an SRAM row cache in heterogeneous 3-D DRAM architecture using TSV

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract