Design and analysis of efficient application-specific on-line page replacement techniques

Authors:
Virgil Andronache;Edwin H.-M. Sha;Nelson L. Passos
Affiliations:
Dept of Computer Science and Engineering, University of Notre Dame, Notre Dame, Indiana;Dept of Computer Science and Engineering, University of Notre Dame, Notre Dame, Indiana;Department of Computer Science, Midwestern State University, Wichita Falls, Texas
Venue:
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Year:
2000

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Abstract

The trend in computer performance over the last 20 years has indicated that the memory performance constitutes a bottlneck for the overall system performance. As a result, smaller, faster memories have been introduced to hide the speed differential between the CPU and memory. From the beginning of this process, an essential question has been the determination of which part of main memory should reside in the faster memory at each instant. Several on-line and off-line algorithms have been introduced, the best known and most used of which are LRU and MIN respectively. This paper introduces a new approach to page replacement in that it allows the compiler to enter the decision process. In introducing compiler help to page replacement, information available at compile time is passed on to new hardware added to the regular memory, with the overall effect of markedly decreasing overall memory access time.