A new technique for estimating lower bounds on latency for high level synthesis

Authors:
Helvio P. Peixoto;Margarida F. Jacome
Affiliations:
Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX;Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX
Venue:
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Year:
2000

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Abstract

In this paper we present a novel and fast estimation technique that produces tight latency lower bounds for Data Flow Graphs representing time critical segments of the application of interest. Our proposed technique can be used to compute a tighter earliest scheduling step for nodes (operations) in the Data Flow Graph and thus be used to improve the result quality of any technique requiring the computation of such ASAP values.