Practical low power digital VLSI design
Practical low power digital VLSI design
Power consumption of parallel spread spectrum correlator architectures
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Low-power CMOS wireless communications: a wideband CDMA system design
Low-power CMOS wireless communications: a wideband CDMA system design
Spreading codes for direct sequence CDMA and wideband CDMA cellular networks
IEEE Communications Magazine
Wideband DS-CDMA for next-generation mobile communications systems
IEEE Communications Magazine
UMTS/IMT-2000 based on wideband CDMA
IEEE Communications Magazine
A Low Power Correlator for CDMA Wireless Systems
Journal of VLSI Signal Processing Systems
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The complex valued matched filter correlators consume maximum power in the DS/SS CDMA receivers. These correlators accumulate 1024 samples lying in the range -7 to +7. This accumulation needs 3 data bits, 1 sign bit and 10 extra bits for overflow. Hence, the correlator can be implemented as a cascade of 4-bit full adder and a 10-bit incrementer. As a ripple carry adder (RCA) consumes the least power among all the existing adder architectures, we have implemented the 4-bit adder as a RCA. Previous incrementers were implemented as ripple counters. In this paper we propose a novel incrementer which is faster than a ripple counter based incrementer. Hence, it can be operated at a reduced voltage resulting in considerable power reduction. The incrementer is implemented using multiplexers, AND gates and TSPC registers. The ripple-counter correlator and the proposed incrementer correlator were laid out in MAGIC using 0.5µ CMOS technology followed by power estimation using HSPICE. It is shown that the proposed architecture requires 50% less power than a ripple counter based design.