MPEG: a video compression standard for multimedia applications
Communications of the ACM - Special issue on digital multimedia systems
Embedded DRAM architectural trade-offs
Proceedings of the conference on Design, automation and test in Europe
Digital Video: An introduction to MPEG-2
Digital Video: An introduction to MPEG-2
Low-power DV encoder architecture for digital CMOS camcorder
ICASSP '99 Proceedings of the Acoustics, Speech, and Signal Processing, 1999. on 1999 IEEE International Conference - Volume 04
Design considerations of the video compression system of the new DV camcorder standard
IEEE Transactions on Consumer Electronics
Fast motion vector estimation using multiresolution-spatio-temporal correlations
IEEE Transactions on Circuits and Systems for Video Technology
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A low-power, large-scale parallel video compression architecture for asingle-chip digital CMOS camera is discussed in this paper. Thisarchitecture is designed for highly computationally intensive image andvideo processing tasks necessary to support video compression. Two designsof this architecture, an MPEG2 encoder and a DV encoder, are presented. Atan image resolution of 640 × 480 pixels (MPEG2) and 720 × 576 (DV)and a frame rate of 25 to 30 frames per second, a computational throughputof up to 1.8 billion operations per second (BOPS) is required. This issupported in the proposed architecture using a 40 MHz clock and an array of40 to 45 parallel processors implemented in a 0.2 μm CMOS technology andwith a 1.5 V supply voltage. Power consumption is significantly reducedthrough the single-chip integration of the CMOS photo sensors, the embeddedDRAM technology, and the proposed pipelined parallel processors. Theparallel processors consume approximately 45 mW of power resulting a powerefficiency of 40 BOPS/W.