Design of a Temporal Learning Chip for Signal Generation and Classification

  • Authors:
  • Fathi M. Salam;Hwa-Joon Oh

  • Affiliations:
  • Circuits, Systems, and Artificial Neural Networks (CSANN) Laboratory, Department of Electrical Engineering, Michigan State University, East Lansing, MI, 48824 salam@ee.msu.edu;Hyundai Electronics America, 3103 North First Street, San Jose, CA, 95123 hjoh@HEA.COM

  • Venue:
  • Analog Integrated Circuits and Signal Processing - Special issue on Learning on Silicon
  • Year:
  • 1999

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Abstract

The design and analog VLSI implementation of a recurrent neural network with integrated temporal learning is presented. The learning algorithm is forward in time, and is implemented strictly as instantaneous, local weight updates. PSpice simulations of networks with 4 to 6 neurons demonstrate robust learning of trajectory generation and classification tasks. A scalable 2-D VLSI architecture is described and a prototupe 4-neuron recurrent neural network with learning has subsequently been fabricated in MOSIS TinyChip 2 micron technology. Experimental results of the chip validate the learning performance with convergence in the millisecond range. Specific experimental results of learning circular and figure-8 dynamic trajectories are included.