Variability-aware robust design space exploration of chip multiprocessor architectures
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
ACM Transactions on Embedded Computing Systems (TECS)
| Hi-index | 0.00 |
It is clear by now that scaling for CMOS will ultimately hit a roadblock, and require a radical change in fundamental device technology. And yet--we continue to make progress in making impressively small MOSFET devices, at 70nm, 50nm, 20nm.Suppose we can actually get to a 70nm or 50nm or smaller technology, where one device is only a few hundred atoms across. What might life be like down here? How (and why) do the lab versions of these devices work today? And what obstacles exist to using them in real circuits, on real chips? Can we really make wires and pins and other interconnect? Can we manufacture them reliably?And what happens out beyond this inevitable end-of-scaling barrier? What options have we for new device paradigms.Our three invited speakers will fearlessly speculate on what might lie ahead on this wild frontier from three different technical perspectives: highly scaled devices themselves, issues with highly scaled circuits and interconnect, and devices that might actually work out beyond the scaling limit.