Bit-level arithmetic optimization for carry-save additions

Authors:
Kei-Yong Khoo;Zhan Yu;Alan N. Willson, Jr.
Affiliations:
Integrated Circuits and Systems Laboratory, University of California, Los Angeles, CA;Integrated Circuits and Systems Laboratory, University of California, Los Angeles, CA;Integrated Circuits and Systems Laboratory, University of California, Los Angeles, CA
Venue:
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Year:
1999

Citing 2
Cited 1

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Power Optimization of Parallel Multipliers in Systems with Variable Word-Length

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Abstract

This paper addresses the bit-level optimization of carry-save adder (CSA) arrays when the operands are of unequal wordlength (such as in some datapaths in digital signal processing circuits). We first show that by relaxing the carry-save representation to allow for more than two signals per bit position, we gain flexibility in the bit-level implementation of CSA arrays that can be exploited to achieve a more efficient design. We then propose algorithms to optimize a single adder array at the bit-level. In addition, we proposed a heuristic to optimize a series of adder arrays that might occur in a datapath. We have applied our algorithms to the optimization of high-speed digital FIR filters and have achieved 15% to 30% savings (weighted cost) in the overall filter implementation array in comparison to the standard carry-save implementation.