Lambda lifting: transforming programs to recursive equations
Proc. of a conference on Functional programming languages and computer architecture
The g-machine: a fast, graph-reduction evaluator
Proc. of a conference on Functional programming languages and computer architecture
Functional programing and the logical variable
POPL '85 Proceedings of the 12th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
NORMA: a graph reduction processor
LFP '86 Proceedings of the 1986 ACM conference on LISP and functional programming
Performance studies of a Prolog machine architecture
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Efficient compilation of lazy evaluation
SIGPLAN '84 Proceedings of the 1984 SIGPLAN symposium on Compiler construction
Functional Programming
Performance measurement of a G-machine implementation
Proceedings of the Workshop on Graph Reduction
Compiling a functional language
LFP '84 Proceedings of the 1984 ACM Symposium on LISP and functional programming
Super-combinators a new implementation method for applicative languages
LFP '82 Proceedings of the 1982 ACM symposium on LISP and functional programming
Keeping jump instructions out of the pipeline of a RISC-like computer
ACM SIGARCH Computer Architecture News
The spineless tagless G-machine
FPCA '89 Proceedings of the fourth international conference on Functional programming languages and computer architecture
Lively linear Lisp: “look ma, no garbage!”
ACM SIGPLAN Notices
POPL '95 Proceedings of the 22nd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
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The G-machine is a language-directed processor architecture designed to support graph reduction as a model of computation. It can carry out lazy evaluation of functional language programs and can evaluate programs in which logical variables are used. To support these language features, the abstract machine requires tagged memory and executes some rather complex instructions, such as to evaluate a function application.This paper explores an implementation of the G-machine as a high performance RISC architecture. Complex instructions can be represented by RISC code without experiencing a large expansion of code volume. The instruction pipeline is discussed in some detail. The processor is intended to be integrated into a standard, 32-bit memory architecture. Tagged memory is supported by aggregating data with tags in a cache.