Energy-efficient code generation for DSP56000 family (poster session)

Authors:
Sathishkumar Udayanarayanan;Chaitali Chakrabarti
Affiliations:
Center for Low Power Electronics, Department of Electrical Engineering, Tempe, AZ;Center for Low Power Electronics, Department of Electrical Engineering, Tempe, AZ
Venue:
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Year:
2000

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Abstract

This paper presents a procedure to generate energy-efficient code for the Motorola DSP56K processor based on increasing the packing efficiency and minimizing the number of address instructions. The key features are a novel scheduling algorithm that reduces the dependencies between instructions, a register allocation algorithm that spills variables based on their packability, and an address code generation algorithm that minimizes the number of additional instructions. The size of the code generated by this procedure is on the average 45% (25%) smaller than that generated by Motorola's g56K (SPAM).