Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
Fault tolerance in FFT arrays: time redundancy approaches
Journal of VLSI Signal Processing Systems
Parallel reduced area multipliers
Journal of VLSI Signal Processing Systems - Special issue on application-specific array processors
Division Algorithms and Implementations
IEEE Transactions on Computers
VLSI Concurrent Error Correcting Adders and Multipliers
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Power Consumption in Fast Dividers Using Time Shared TMR
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Fast IEEE Rounding for Division by Functional Iteration
Fast IEEE Rounding for Division by Functional Iteration
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Iterative division algorithms based on multiplication are popular because they are fast and may utilize an already existing hardware multiplier. Two popular methods based on multiplication are Newton-Raphson and Goldschmidt's algorithm. To achieve concurrent error correction, Time Shared Triple Modular Redundancy (TSTMR) may be applied to both kinds of dividers. The hardware multiplier is divided into thirds, and the rest of the divider logic replicated around each part, to provide three independent dividers. While this reduces the size of the fault-tolerant dividers over that of traditional TMR, latency may be increased. However, both division algorithms can be modified to use lower precision multiplications during the early iterations. This saves multiply cycles and, hence, produces a faster divider.