VISION: VHDL induced schematic imaging on net-lists

Authors:
R. K. Chun;K.-J. Chang;L. P. McNamee
Affiliations:
TRW Electronic Systems Group, UCLA Computer Science Department;UCLA Computer Science Department;UCLA Computer Science Department
Venue:
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Year:
1987

Citing 2
Cited 1

Introduction to VLSI Systems

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An algorithm for automatic line routing on Schematic Drawings

DAC '75 Proceedings of the 12th Design Automation Conference

HERESY: a hybrid approach to automatic schematic generation

EURO-DAC '91 Proceedings of the conference on European design automation

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Abstract

This paper describes a system capable of generating schematic diagrams for gate-level digital logic circuits given only their net-list descriptions in the VHSIC (Very High Speed Integrated Circuit) Hardware Description Language (VHDL). A combination of algorithmic and heuristic methods are employed to synthesize a schematic drawing which is as aesthetically pleasing and functionally readable to human designers as possible. A methodology for generating schematics which contain feedback loops is presented