Layout Dependent Matching Analysis of CMOS Circuits

Authors:
Kenichi Okada;Hidetoshi Onodera;Keikichi Tamaru
Affiliations:
Department of Communications and Computer Engineering, Kyoto University, Kyoto-shi, 606--8501 Japan;Department of Communications and Computer Engineering, Kyoto University, Kyoto-shi, 606--8501 Japan;Department of Communications and Computer Engineering, Kyoto University, Kyoto-shi, 606--8501 Japan
Venue:
Analog Integrated Circuits and Signal Processing - Analog circuit techniques and related topics
Year:
2000

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Abstract

Layout has strong influence on matching properties of a circuit. Current matching models, which characterize both local random non-uniformities and global systematic non-uniformities stochastically, are not adequate for the matching analysis taking the effect of layout realization into account. In order to consider topological information of layout into matching analysis, we propose a matching model which treats the random and systematic components separately. Also, we characterize the micro-loading effect, which modulates fabricated line-width according to the local density of layout patterns, into matching analysis. With these two techniques, we can perform matching analysis of CMOS circuits taking layout information into account.