Integrated Circuits of Map Chaos Generators

  • Authors:

  • Hidetoshi Tanaka;Shigeo Sato;Koji Nakajima

  • Affiliations:

  • Laboratory for Electronic Intelligent Systems, Research Institute of Electrical Communication, Tohoku University, Sendai-shi, 980–8577, Japan;Laboratory for Electronic Intelligent Systems, Research Institute of Electrical Communication, Tohoku University, Sendai-shi, 980–8577, Japan;Laboratory for Electronic Intelligent Systems, Research Institute of Electrical Communication, Tohoku University, Sendai-shi, 980–8577, Japan

  • Venue:
  • Analog Integrated Circuits and Signal Processing - Analog circuit techniques and related topics
  • Year:
  • 2000

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Abstract

A chaotic noise is one of the most important implements for information processing such as neural networks. It has been suggested that chaotic neural networks have high performance ability for information processing. In this paper, we report two designs of a compact chaotic noise generator for large integration circuits using CMOS technology. The chaotic noise is generated using map chaos. We design both of the logistic map type and the tent map type circuits. These chaotic noise generators are compact as compared with the other circuits. The results show that the successful chaotic operations of the circuits because of the positive Lyapunov number. We calculate the Lyapunov exponents to certify the results of the chaotic operations. However, it is hard to estimate its accurate number for noisy data using the conventional method. And hence, we propose the modified calculation of the Lyapunov exponent for noisy data. These two circuits are expected to be utilized for various applications.