Integrated Circuit Implementation of a Compact Discrete-Time Chaos Generator

Authors:
V. D. Juncu;M. Rafiei-Naeini;P. Dudek
Affiliations:
School of Electrical and Electronic Engineering, University of Manchester, Manchester, UK M60 1QD;School of Electrical and Electronic Engineering, University of Manchester, Manchester, UK M60 1QD;School of Electrical and Electronic Engineering, University of Manchester, Manchester, UK M60 1QD
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2006

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Abstract

A discrete-time chaos generator implemented with two nonlinear circuit cells has been fabricated in a 0.6 驴m CMOS technology. Each cell is creating a function (map) which allows a chaos signal to be generated. Measurements of the chip were performed with a supply voltage of 5 V, up to a frequency of 2.5 MHz. A bifurcation diagram of the circuit and the Lyapunov exponent calculation are presented. The size of the generator layout (without the switches) is 32 脳 19 驴 m which makes it suitable for applications where many chaos signal generators are required on a single chip.