A vector-pipeline DSP for low-rate videophones

  • Authors:

  • Kazutoshi Kobayashi;Makoto Eguchi;Takuya Iwahashi;Takehide Shibayama;Xiang Li;Kousuke Takai;Hidetoshi Onodera

  • Affiliations:

  • Graduate School of Informatics, Kyoto University, Kyoto 606-8501, Japan;Graduate School of Informatics, Kyoto University, Kyoto 606-8501, Japan;Graduate School of Informatics, Kyoto University, Kyoto 606-8501, Japan;Graduate School of Informatics, Kyoto University, Kyoto 606-8501, Japan;Graduate School of Informatics, Kyoto University, Kyoto 606-8501, Japan;Graduate School of Informatics, Kyoto University, Kyoto 606-8501, Japan;Graduate School of Informatics, Kyoto University, Kyoto 606-8501, Japan

  • Venue:
  • Proceedings of the 2001 Asia and South Pacific Design Automation Conference
  • Year:
  • 2001

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Abstract

We propose a vector-pipeline processor VP-DSP for low-rate videophones, which can encode and decode 10 frames/sec. of QCIF through a 29.2kbps low-rate line. We have already fabricated a VP-DSP LSI by a 0.35 um CMOS process. The area of the VP-DSP core is 4.2mm. It works properly at 25MHz/1.6V with the power dissipation of 49mW. Its peak performance is up to 400MOPS, 8.2GOPS/W.