Pattern Noise in the Frequency ΔΣ Modulator

Authors:
Mats E. HØvin;Dag T. Wisland;Jan T. Marienborg;Tor S. Lande;Yngvar Berg
Affiliations:
Microelectronic System Group, Department of Informatics, University of Oslo, Gaustadalle´en 23, Blindern, N-0316 Oslo, Norway;Microelectronic System Group, Department of Informatics, University of Oslo, Gaustadalle´en 23, Blindern, N-0316 Oslo, Norway;Microelectronic System Group, Department of Informatics, University of Oslo, Gaustadalle´en 23, Blindern, N-0316 Oslo, Norway;Microelectronic System Group, Department of Informatics, University of Oslo, Gaustadalle´en 23, Blindern, N-0316 Oslo, Norway;Microelectronic System Group, Department of Informatics, University of Oslo, Gaustadalle´en 23, Blindern, N-0316 Oslo, Norway
Venue:
Analog Integrated Circuits and Signal Processing - Special issue on selected papers from the NORCHIP 1999 conference
Year:
2001

Citing 1
Cited 1

LSI/VLSI testability design

LSI/VLSI testability design

Subthreshold parallel FM-to-digital Δ-Σ converter with output-bit-stream addition by interleaving

IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2008 custom integrated circuits conference (CICC 2008)

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Abstract

In this paper, we show that the first-order frequency delta–sigma modulator is equivalent to a traditional delta–sigma modulator with respect to pattern noise. We further propose two techniques for reducing the effect of pattern noise. The first technique is based on time-domain dithering which is implemented by adding white phase noise to the FM signal. The second technique is based on locating the narrow dynamic range that may be in this kind of modulators, in a pattern noise valley. This technique can utilize pattern noise to make the modulator provide significantly higher digital resolution than the white quantization noise model predicts. Finally, the theory is verified by measurements.