Communication systems engineering
Communication systems engineering
Digital signal processing (3rd ed.): principles, algorithms, and applications
Digital signal processing (3rd ed.): principles, algorithms, and applications
Pattern Noise in the Frequency ΔΣ Modulator
Analog Integrated Circuits and Signal Processing - Special issue on selected papers from the NORCHIP 1999 conference
An Analog Multi-Tone Signal Generator for Built-In Self-Test Applications
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Continuous-Time Digital Signal Processors
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
Increasing Fault Tolerance to Multiple Upsets Using Digital Sigma-Delta Modulators
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Reliable Digital Circuits Design using Sigma-Delta Modulated Signals
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
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Single and parallel subthreshold frequency-modulation-to-digital Δ-Σ modulators (FDSMs) have been implemented in a standard 90-nm CMOS technology. Theoretical and measured results are presented for both topologies. The 512-stage parallel FDSM adopts a tunable delay line and achieves bit-stream addition by interleaving at the output stage. This architecture, with respect to the conventional parallel FDSM, reduces power, area, and complexity at the cost of using clocks with higher speed in its output stage. In addition, compared to the single FDSM, the parallel converter shows an improvement in signal-to-quantization-noise ratio of more than 25 dB at supply voltages as low as 300 mV.