Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
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Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
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Formal Methods in System Design - Special issue on computer-aided verification: special methods II
Computer-aided verification of coordinating processes: the automata-theoretic approach
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Information and Computation
Checking that finite state concurrent programs satisfy their linear specification
POPL '85 Proceedings of the 12th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Symbolic Model Checking
Memory Efficient Algorithms for the Verification of Temporal Properties
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Efficient omega-Regular Language Containment
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
Computing strongly connected components in a linear number of symbolic steps
SODA '03 Proceedings of the fourteenth annual ACM-SIAM symposium on Discrete algorithms
From linear time to branching time
ACM Transactions on Computational Logic (TOCL)
Automata-theoretic model checking revisited
VMCAI'07 Proceedings of the 8th international conference on Verification, model checking, and abstract interpretation
Symbolic computation of strongly connected components and fair cycles using saturation
Innovations in Systems and Software Engineering
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Frontiers of Computer Science: Selected Publications from Chinese Universities
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We describe a new heuristic for detecting bad cycles (reachable cycles that are not confined within one or another designated sets of model states), a fundamental operation for model-checking algorithms. It is a variation on a standard implementation of the Emerson-Lei algorithm, which our experimental data suggests can result in a significant speed-up for verification runs that pass. We conclude that this heuristic can be used to advantage on “mature” designs for which the anticipated result of the verification is pass.