The B-book: assigning programs to meanings
The B-book: assigning programs to meanings
A refinement calculus for the synthesis of verified hardware descriptions in VHDL
ACM Transactions on Programming Languages and Systems (TOPLAS)
The Designer's Guide to VHDL
Hardware verification and beyond: using b at AWE
B'07 Proceedings of the 7th international conference on Formal Specification and Development in B
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We have demonstrated that clocked synchronous logic can be developed within a formal software framework. The advantage of this approach is that it allows abstraction, animation and proof of refinement. The B-Toolkit supports these activities and has a VHDL generator. The validation tests can be agreed and carried out during animation early in the development cycle (a common technique in software). Proof of refinement may be important for critical applications. The AWE plans to explore the proof of their Arming System Processor with the techniques over-viewed in this paper.