A new simulator workbench for comparing SIMD processing element architectures

• Authors: Todd C. Marek
• Venue: ACM-SE 30 Proceedings of the 30th annual Southeast regional conference
• Year: 1992

The impact of machine structure on system performance is a critical consideration in designing highly integrated SIMD architectures. This issue is affected by PE granularity, PE complexity, and interconnection structure. Detailed analysis of the issues related to this structure/performance relationship is relevant in developing new massively parallel architectures. To meet this need, a simulator workbench which can be used to quantitatively evaluate the performance of a wide range of machine structures is presented in this paper. The set of PE granularities supported includes 1, 4, 8, and 16-bit processors. The simulator workbench also provides support for evaluating the functionality provided by different features included in an SIMD PE. Features include floating point operation support, multiplication support, local address modification, and support for generating flags during computation. An analysis of the impact of various I/O and communication path widths is also possible.Floating point support is provided in the form of an exponent register and a mantissa unit. Multiplication is supported by a recoding unit that examines two multiplier bits and recodes them in such a way that a partial product of the multiplicand and the two multiplier bits can be generated with only a single n-bit addition. Communication and I/O path widths are examined for each granularity, and the amount of time spent in communication and data I/O can be isolated for any application. The impact of local address modification is isolated, and flag sets are also investigated. Overall performance, communication balance, PE and feature utilization, and operand length are monitored using the workbench, and are used to assess the merits of the various granularities and feature sets.